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SAMOS
2004
Springer
15 years 5 months ago
A Novel Data-Path for Accelerating DSP Kernels
A high-performance data-path to implement DSP kernels is proposed in this paper. The data-path is based on a flexible, universal, and regular component to optimally exploiting both...
Michalis D. Galanis, George Theodoridis, Spyros Tr...
FCCM
2003
IEEE
133views VLSI» more  FCCM 2003»
15 years 5 months ago
Floating Point Unit Generation and Evaluation for FPGAs
Most commercial and academic floating point libraries for FPGAs provide only a small fraction of all possible floating point units. In contrast, the floating point unit generat...
Jian Liang, Russell Tessier, Oskar Mencer
ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
15 years 4 months ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Ho-Seop Kim, James E. Smith
ASAP
2007
IEEE
134views Hardware» more  ASAP 2007»
15 years 1 months ago
Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
David Montgomery, Ali Akoglu
COMCOM
2006
93views more  COMCOM 2006»
14 years 12 months ago
On scalability properties of the Hi3 control plane
The Host Identity Indirection Infrastructure (Hi3) is a general-purpose networking architecture, derived from the Internet Indirection Infrastructure (i3) and the Host Identity Pr...
Dmitry Korzun, Andrei Gurtov