Sciweavers

248 search results - page 18 / 50
» Layered Switching for Networks on Chip
Sort
View
INFOCOM
1999
IEEE
15 years 4 months ago
A Model for Window Based Flow Control in Packet-Switched Networks
Recently, networks have increased rapidly both in scale and speed. Problems related to the control and management are of increasing interest. The average throughput and end-to-end ...
Xiaowei Yang
HPCA
2003
IEEE
16 years 4 days ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
TCAD
2010
124views more  TCAD 2010»
14 years 6 months ago
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...
Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
14 years 9 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim
IEEEPACT
2008
IEEE
15 years 6 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang