248 search results - page 27 / 50 » Layered Switching for Networks on Chip |
GECCO
2010
Springer
15 years 4 months ago
2010
Springer
The Spidergon interconnection network has become popular recently in multiprocessor systems on chips. To the best of our knowledge, algorithms for collective communications (CC) h...
IJCAI
1997
15 years 1 months ago
1997
This paper describes an evolvable hardware (EHW) system for generalized neural network learning. We have developed an ASIC VLSI chip, which is a building block to configure a scal...
IJCNN
2007
IEEE
15 years 6 months ago
2007
IEEE
- We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motiva...
104
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HSNMC
2004
Springer
15 years 5 months ago
2004
Springer
Multiprotocol Label Switching (MPLS) is emerging as a flexible technology that can transport voice, IPv4, IPv6, layer 2 services (Frame Relay, ATM, Ethernet, etc.), and even PDH an...
121
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JSAC
2008
14 years 11 months ago
2008
Abstract-- In WDM all-optical networks where electrical regeneration is not available, physical impairments due to propagation in the fibers, amplifier noise, and leaks between cha...