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» Learning to Construct Fast Signal Processing Implementations
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ICASSP
2009
IEEE
15 years 3 months ago
Generating high performance pruned FFT implementations
We derive a recursive general-radix pruned Cooley-Tukey fast Fourier transform (FFT) algorithm in Kronecker product notation. The algorithm is compatible with vectorization and pa...
Franz Franchetti, Markus Püschel
VTS
2006
IEEE
98views Hardware» more  VTS 2006»
15 years 5 months ago
Iterative OPDD Based Signal Probability Calculation
This paper presents an improved method to accurately estimate signal probabilities using ordered partial decision diagrams (OPDDs) [Kodavarti 93] for partial representation of the...
Avijit Dutta, Nur A. Touba
DATE
2009
IEEE
135views Hardware» more  DATE 2009»
15 years 6 months ago
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
Reconfigurable Architectures are good candidates for application accelerators that cannot be set in stone at production time. FPGAs however, often suffer from the area and perfor...
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
ICASSP
2010
IEEE
14 years 11 months ago
High frame rate Motion Compensated Frame Interpolation in High-Definition video processing
Numerous MCFI methods have been proposed to increase the frame rate in the past ten years. However, these methods usually focus on how to double the frame rate and involve complex...
Yen-Lin Lee, Truong Nguyen
ESANN
2008
15 years 1 months ago
Parallel asynchronous neighborhood mechanism for WTM Kohonen network implemented in CMOS technology
In this paper we present an original neighborhood mechanism for WTM self-organizing Kohonen map implemented in CMOS 0.18 m process. Proposed mechanism is an asynchronous circuit an...
Marta Kolasa, Rafal Dlugosz