Sciweavers

33 search results - page 4 / 7
» Leveraging 3D Technology for Improved Reliability
Sort
View
TVLSI
2010
13 years 28 days ago
Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding
By storing more than one bit in each memory cell, multi-level per cell (MLC) NAND flash memories are dominating global flash memory market due to their appealing storage density ad...
Shu Li, Tong Zhang
DAC
2008
ACM
13 years 8 months ago
Analog parallelism in ring-based VCOs
The performance advantages in parallel ring-based VCOs are explored. When the number of VCOs is doubled, the parallel VCOs enhance phase noise by 3dB, and the within-chip process-...
Daeik D. Kim, Choongyeun Cho, Jonghae Kim
ASPDAC
2007
ACM
122views Hardware» more  ASPDAC 2007»
13 years 10 months ago
Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect
Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper int...
Arthur Nieuwoudt, Mosin Mondal, Yehia Massoud
VR
2009
IEEE
319views Virtual Reality» more  VR 2009»
14 years 1 months ago
Virtual Heliodon: Spatially Augmented Reality for Architectural Daylighting Design
We present an application of interactive global illumination and spatially augmented reality to architectural daylight modeling that allows designers to explore alternative design...
Yu Sheng, Theodore C. Yapo, Christopher Young, Bar...
CODES
2011
IEEE
12 years 6 months ago
Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must b...
Benny Akesson, Po-Chun Huang, Fabien Clermidy, Den...