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» Leveraging parallel nesting in transactional memory
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VMCAI
2009
Springer
15 years 4 months ago
An Abort-Aware Model of Transactional Programming
There has been a lot of recent research on transaction-based concurrent programming, aimed at offering an easier concurrent programming paradigm that enables programmers to better...
Kousha Etessami, Patrice Godefroid
IPPS
2009
IEEE
15 years 4 months ago
Using hardware transactional memory for data race detection
Abstract—Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable...
Shantanu Gupta, Florin Sultan, Srihari Cadambi, Fr...
PPOPP
2006
ACM
15 years 3 months ago
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hu...
IEEEPACT
2008
IEEE
15 years 4 months ago
Scalable and reliable communication for hardware transactional memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...
ISCA
2007
IEEE
149views Hardware» more  ISCA 2007»
15 years 3 months ago
An effective hybrid transactional memory system with strong isolation guarantees
We propose signature-accelerated transactional memory (SigTM), a hybrid TM system that reduces the overhead of software transactions. SigTM uses hardware signatures to track the r...
Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Au...