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121
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ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
15 years 10 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
101
Voted
FPL
2006
Springer
91views Hardware» more  FPL 2006»
15 years 5 months ago
Multi-Bit Carry Chains for High-Performance Reconfigurable Fabrics
Ripple-carry architectures are the norm in today's reconfigurable fabrics. They are simple, require minimal routing, and are easily formed across arbitrary cells in a fabric....
Michael T. Frederick, Arun K. Somani
MSCS
2007
125views more  MSCS 2007»
15 years 1 months ago
On categorical models of classical logic and the Geometry of Interaction
It is well-known that weakening and contraction cause na¨ıve categorical models of the classical sequent calculus to collapse to Boolean lattices. In previous work, summarized b...
Carsten Führmann, David J. Pym
ICSE
2004
IEEE-ACM
16 years 1 months ago
Runtime Verification of Statechart Implementations
Our paper introduces a runtime verification framework for concurrent monitoring of applications specified by UML statecharts. The approach offers a considerable degree of granulari...
Gergely Pintér, István Majzik
TPHOL
2005
IEEE
15 years 7 months ago
From PSL to LTL: A Formal Validation in HOL
Using the HOL theorem prover, we proved the correctness of a translation from a subset of Accellera’s property specification language PSL to linear temporal logic LTL. Moreover,...
Thomas Tuerk, Klaus Schneider