1929 search results - page 127 / 386 » Load Balancing with Memory |
148
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ISCA
2009
IEEE
15 years 9 months ago
2009
IEEE
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
130
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HPCA
2002
IEEE
16 years 3 months ago
2002
IEEE
The increasing performance gap between processors and memory will force future architectures to devote significant resources towards removing and hiding memory latency. The two ma...
131
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EUROMICRO
2007
IEEE
15 years 9 months ago
2007
IEEE
Reliable Server Pooling (RSerPool) is a protocol framework for server redundancy and session failover, currently still under standardization by the IETF RSerPool WG. Server redund...
116
Voted
IPPS
2007
IEEE
15 years 9 months ago
2007
IEEE
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
105
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PLDI
1999
ACM
15 years 7 months ago
1999
ACM
Load-reuse analysis finds instructions that repeatedly access the same memory location. This location can be promoted to a register, eliminating redundant loads by reusing the re...