1929 search results - page 128 / 386 » Load Balancing with Memory |
138
click to vote
MICRO
2003
IEEE
15 years 8 months ago
2003
IEEE
With faster CPU clocks and wider pipelines, all relevant microarchitecture components should scale accordingly. There have been many proposals for scaling the issue queue, registe...
107
click to vote
SERP
2007
15 years 4 months ago
2007
Escape analysis can improve the speed and memory efficiency of garbage collected languages by allocating objects to the call stack, but an offline analysis will potentially interf...
126
click to vote
SASP
2009
IEEE
15 years 10 months ago
2009
IEEE
—With the appearance of massively parallel and inexpensive platforms such as the G80 generation of NVIDIA GPUs, more real-life applications will be designed or ported to these pl...
126
click to vote
ISCA
2005
IEEE
15 years 8 months ago
2005
IEEE
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
DAC
2009
ACM
16 years 4 months ago
2009
ACM
In this paper we introduce a new method of performing direct solution of the harmonic balance Jacobian. For examples with moderate number of harmonics and moderate to strong nonli...