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» Location cache: a low-power L2 cache system
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IPPS
1998
IEEE
15 years 1 months ago
Code Transformations for Low Power Caching in Embedded Multimedia Processors
In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processin...
Chidamber Kulkarni, Francky Catthoor, Hugo De Man
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
15 years 3 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
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ISHPC
1999
Springer
15 years 1 months ago
Utilization of Cache Area in On-Chip Multiprocessor
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
Hitoshi Oi, N. Ranganathan
EDBT
2006
ACM
157views Database» more  EDBT 2006»
15 years 9 months ago
Caching Complementary Space for Location-Based Services
In this paper, we propose a novel client-side, multi-granularity caching scheme, called "Complementary Space Caching" (CS caching), for location-based services in mobile ...
Ken C. K. Lee, Wang-Chien Lee, Baihua Zheng, Jianl...
DATE
2003
IEEE
141views Hardware» more  DATE 2003»
15 years 2 months ago
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
Mahesh Mamidipaka, Nikil D. Dutt