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» Logic synthesis for PLA with 2-input logic elements
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FPGA
2000
ACM
161views FPGA» more  FPGA 2000»
15 years 1 months ago
The effect of LUT and cluster size on deep-submicron FPGA performance and density
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...
Elias Ahmed, Jonathan Rose
DATE
2002
IEEE
206views Hardware» more  DATE 2002»
15 years 2 months ago
Accurate Area and Delay Estimators for FPGAs
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
Anshuman Nayak, Malay Haldar, Alok N. Choudhary, P...
ASAP
2007
IEEE
123views Hardware» more  ASAP 2007»
14 years 11 months ago
Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors
FPGA (Field Programmable Gate Array) based reconfigurable processor has been shown to meet the increasingly challenging performance targets and shorter time-to-market pressures. I...
Siew Kei Lam, Thambipillai Srikanthan
DLOG
2006
14 years 11 months ago
Tableau Caching for Description Logics with Inverse and Transitive Roles
Abstract. Modern description logic (DL) reasoners are known to be less efficient for DLs with inverse roles. The current loss of performance is largely due to the missing applicabi...
Yu Ding, Volker Haarslev
SIGLEX
1991
15 years 1 months ago
Logical Structures in the Lexicon
The lexical entry for a word must contain all the information needed to construct a semantic representation for sentences that contain the word. Because of that requirement, the f...
John F. Sowa