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DAC
2009
ACM
15 years 7 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
144
Voted
TSE
2011
134views more  TSE 2011»
14 years 7 months ago
Verifying the Evolution of Probability Distributions Governed by a DTMC
— We propose a new probabilistic temporal logic iLTL which captures properties of systems whose state can be represented by probability mass functions (pmf’s). Using iLTL, we c...
YoungMin Kwon, Gul A. Agha
DAC
2005
ACM
16 years 1 months ago
Incremental exploration of the combined physical and behavioral design space
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Z...
100
Voted
CCS
2009
ACM
16 years 29 days ago
D-algebra for composing access control policy decisions
This paper proposes a D-algebra to compose decisions from multiple access control policies. Compared to other algebrabased approaches aimed at policy composition, D-algebra is the...
Qun Ni, Elisa Bertino, Jorge Lobo
94
Voted
EWSN
2010
Springer
15 years 9 months ago
F-LQE: A Fuzzy Link Quality Estimator for Wireless Sensor Networks
Abstract. Radio Link Quality Estimation (LQE) is a fundamental building block for Wireless Sensor Networks, namely for a reliable deployment, resource management and routing. Exist...
Nouha Baccour, Anis Koubaa, Habib Youssef, Maissa ...