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» Loop Striping: Maximize Parallelism for Nested Loops
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JPDC
2008
108views more  JPDC 2008»
14 years 10 months ago
Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP
Energy saving is becoming one of the major design issues in processor architectures with multiple functional units (FUs). Nested loops are usually the most critical part in multim...
Meikang Qiu, Edwin Hsing-Mean Sha, Meilin Liu, Man...
TVLSI
2008
115views more  TVLSI 2008»
14 years 10 months ago
Outer Loop Pipelining for Application Specific Datapaths in FPGAs
Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. In this work we exten...
Kieron Turkington, Turkington A. Constantinides, K...
NCA
2005
IEEE
15 years 3 months ago
Reducing the Communication Cost via Chain Pattern Scheduling
This paper deals with general nested loops and proposes a novel scheduling methodology for reducing the communication cost of parallel programs. General loops contain complex loop...
Florina M. Ciorba, Theodore Andronikos, Ioannis Dr...
CF
2007
ACM
15 years 2 months ago
Identifying potential parallelism via loop-centric profiling
The transition to multithreaded, multi-core designs places a greater responsibility on programmers and software for improving performance; thread-level parallelism (TLP) will be i...
Tipp Moseley, Daniel A. Connors, Dirk Grunwald, Ra...
IPPS
1999
IEEE
15 years 2 months ago
Cascaded Execution: Speeding Up Unparallelized Execution on Shared-Memory Multiprocessors
Both inherently sequential code and limitations of analysis techniques prevent full parallelization of many applications by parallelizing compilers. Amdahl's Law tells us tha...
Ruth E. Anderson, Thu D. Nguyen, John Zahorjan