17 search results - page 2 / 4 » Loop Transformation Techniques To Aid In Loop Unrolling and ... |
LCTRTS
1999
Springer
13 years 10 months ago
1999
Springer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
VLSID
2009
IEEE
14 years 7 months ago
2009
IEEE
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
CF
2007
ACM
13 years 10 months ago
2007
ACM
The transition to multithreaded, multi-core designs places a greater responsibility on programmers and software for improving performance; thread-level parallelism (TLP) will be i...
SC
1992
ACM
13 years 10 months ago
1992
ACM
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
ICASSP
2008
IEEE
14 years 24 days ago
2008
IEEE
In this paper, we propose a systemic approach for synthesizing field-programmable gate array (FPGA) implementations of fast Fourier transform (FFT) computations. Our approach cons...