52 search results - page 1 / 11 » Low Power BIST Based on Scan Partitioning |
125
Voted
DFT
2005
IEEE
15 years 3 days ago
2005
IEEE
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
ITC
2000
IEEE
15 years 2 months ago
2000
IEEE
A deterministic partitioning technique for fault diagnosis in Scan-Based BIST is proposed. Properties of high quality partitions for improved fault diagnosis times are identified...
ISQED
2005
IEEE
15 years 3 months ago
2005
IEEE
ITC
2003
IEEE
15 years 3 months ago
2003
IEEE
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
86
Voted
ATS
2004
IEEE
15 years 1 months ago
2004
IEEE
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...