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» Low Power Hardware for a High Performance PDA
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CGO
2004
IEEE
15 years 5 months ago
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv...
ICCD
1999
IEEE
110views Hardware» more  ICCD 1999»
15 years 6 months ago
TriMedia CPU64 Architecture
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...
JSAC
2008
125views more  JSAC 2008»
15 years 1 months ago
Nonbinary LDPC Coding for Multicarrier Underwater Acoustic Communication
Recently, multicarrier modulation in the form of orthogonal frequency division multiplexing (OFDM) has been shown feasible for underwater acoustic communications via effective algo...
Jie Huang, Shengli Zhou, Peter Willett
FAST
2011
14 years 5 months ago
CAFTL: A Content-Aware Flash Translation Layer Enhancing the Lifespan of Flash Memory based Solid State Drives
Although Flash Memory based Solid State Drive (SSD) exhibits high performance and low power consumption, a critical concern is its limited lifespan along with the associated relia...
Feng Chen, Tian Luo, Xiaodong Zhang
GLVLSI
2008
IEEE
204views VLSI» more  GLVLSI 2008»
15 years 8 months ago
NBTI resilient circuits using adaptive body biasing
Reliability has become a practical concern in today’s VLSI design with advanced technologies. In-situ sensors have been proposed for reliability monitoring to provide advance wa...
Zhenyu Qi, Mircea R. Stan