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» Low Power Hardware for a High Performance PDA
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FPGA
2009
ACM
154views FPGA» more  FPGA 2009»
15 years 8 months ago
Synthesis of reconfigurable high-performance multicore systems
Reconfigurable high-performance computing systems (RHPC) have been attracting more and more attention over the past few years. RHPC systems are a promising solution for accelerati...
Jason Cong, Karthik Gururaj, Guoling Han
DFT
2009
IEEE
154views VLSI» more  DFT 2009»
15 years 8 months ago
Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip
We propose a framework that allows dual-layer cooperative error control in a nanoscale network-on-chip (NoC), to simultaneously improve reliability, performance and energy efficie...
Qiaoyan Yu, Paul Ampadu
ARITH
2007
IEEE
15 years 8 months ago
P6 Binary Floating-Point Unit
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a tech...
Son Dao Trong, Martin S. Schmookler, Eric M. Schwa...
ICPADS
2007
IEEE
15 years 8 months ago
Federated clusters using the transparent remote Execution (TREx) environment
- Due to the increasing complexity of scientific models, large-scale simulation tools often require a critical amount of computational power to produce results in a reasonable amou...
Richert Wang, Enrique Cauich, Isaac D. Scherson
ISCA
2009
IEEE
159views Hardware» more  ISCA 2009»
15 years 8 months ago
End-to-end register data-flow continuous self-test
While Moore’s Law predicts the ability of semi-conductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in t...
Javier Carretero, Pedro Chaparro, Xavier Vera, Jau...