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TR
2010
128views Hardware» more  TR 2010»
14 years 8 months ago
Strategy for Planning Accelerated Life Tests With Small Sample Sizes
Previous work on planning accelerated life tests has been based on large-sample approximations to evaluate test plan properties. In this paper, we use more accurate simulation met...
Haiming Ma, William Q. Meeker
HPCA
2009
IEEE
16 years 2 months ago
Bridging the computation gap between programmable processors and hardwired accelerators
New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementatio...
Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Sco...
FPGA
2010
ACM
276views FPGA» more  FPGA 2010»
15 years 10 months ago
Accelerating Monte Carlo based SSTA using FPGA
Monte Carlo based SSTA serves as the golden standard against alternative SSTA algorithms, but it is seldom used in practice due to its high computation time. In this paper, we acc...
Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, K...
DATE
2005
IEEE
180views Hardware» more  DATE 2005»
15 years 7 months ago
A Coprocessor for Accelerating Visual Information Processing
Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of mic...
Walter Stechele, L. Alvado Cárcel, Stephan ...
122
Voted
ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
15 years 6 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin