Sciweavers

308 search results - page 31 / 62
» Macromodeling of analog circuits for hierarchical circuit de...
Sort
View
ICCAD
2003
IEEE
105views Hardware» more  ICCAD 2003»
15 years 6 months ago
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
DAC
1997
ACM
15 years 1 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
DAC
1998
ACM
15 years 1 months ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha
ISCAS
2005
IEEE
135views Hardware» more  ISCAS 2005»
15 years 3 months ago
Calculation of intermodulation distortion in CMOS transconductance stage
—The linearity of the transconductance stage is of major concern in the design of some analog circuits. In this paper, Volterra series expansion is used to compute the intermodul...
Lu Liu, Zhihua Wang, Guolin Li
ISCAS
2008
IEEE
118views Hardware» more  ISCAS 2008»
15 years 4 months ago
Low-power IC design for a wireless BCI system
—Integrated circuit (IC) design for a wireless BCI system is put forward in this paper. The system is composed of an electrode, a stimulator, antennas, and an integrated circuit ...
Ming Liu, Hong Chen, Run Chen, Zhihua Wang