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136
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HPCA
2008
IEEE
16 years 6 months ago
2008
IEEE
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
152
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PPOPP
2010
ACM
16 years 3 months ago
2010
ACM
Drawing inspiration from several previous projects, we present an ownership-record-free software transactional memory (STM) system that combines extremely low overhead with unusua...
205
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PPOPP
2006
ACM
15 years 12 months ago
2006
ACM
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
163
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SIGMETRICS
2010
ACM
15 years 10 months ago
2010
ACM
We present S, the first system to provide transparent, lowoverhead application record-replay and the ability to go live from replayed execution. S i...
175
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IEEEPACT
2006
IEEE
15 years 12 months ago
2006
IEEE
Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software....