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ICCAD
2000
IEEE
74views Hardware» more  ICCAD 2000»
15 years 6 months ago
Simultaneous Gate Sizing and Fanout Optimization
This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that ...
Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
ICCAD
1994
IEEE
111views Hardware» more  ICCAD 1994»
15 years 6 months ago
On modeling top-down VLSI design
We present an improved data model that reflects the whole VLSI design process including bottom-up and topdown design phases. The kernel of the model is a static version concept th...
Bernd Schürmann, Joachim Altmeyer, Martin Sch...
DAWAK
2009
Springer
15 years 5 months ago
Skyline View: Efficient Distributed Subspace Skyline Computation
Skyline queries have gained much attention as alternative query semantics with pros (e.g.low query formulation overhead) and cons (e.g.large control over result size). To overcome ...
Jinhan Kim, Jongwuk Lee, Seung-won Hwang
DAWAK
2006
Springer
15 years 5 months ago
Efficient Mining of Large Maximal Bicliques
Abstract. Many real world applications rely on the discovery of maximal biclique subgraphs (complete bipartite subgraphs). However, existing algorithms for enumerating maximal bicl...
Guimei Liu, Kelvin Sim, Jinyan Li
DEEC
2006
IEEE
15 years 5 months ago
A Bottom-Up Workflow Mining Approach for Workflow Applications Analysis
Abstract. Engineering workflow applications are becoming more and more complex, involving numerous interacting business objects within considerable processes. Analysing the interac...
Walid Gaaloul, Karim Baïna, Claude Godart