This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that ...
We present an improved data model that reflects the whole VLSI design process including bottom-up and topdown design phases. The kernel of the model is a static version concept th...
Skyline queries have gained much attention as alternative query semantics with pros (e.g.low query formulation overhead) and cons (e.g.large control over result size). To overcome ...
Abstract. Many real world applications rely on the discovery of maximal biclique subgraphs (complete bipartite subgraphs). However, existing algorithms for enumerating maximal bicl...
Abstract. Engineering workflow applications are becoming more and more complex, involving numerous interacting business objects within considerable processes. Analysing the interac...