562 search results - page 72 / 113 » Mapping a Fault-Tolerant Distributed Algorithm to Systems on... |
SBCCI
2005
ACM
15 years 3 months ago
2005
ACM
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
73
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IPPS
1999
IEEE
15 years 1 months ago
1999
IEEE
The system of equations that govern kinematically redundant manipulators is commonly solved by nding the singular value decomposition (SVD) of the corresponding Jacobian matrix. T...
105
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ICPPW
2007
IEEE
15 years 4 months ago
2007
IEEE
We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-achip, in particular DSP systems, can greatly improve p...
109
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PPOPP
2006
ACM
15 years 3 months ago
2006
ACM
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
HPCN
1995
Springer
15 years 1 months ago
1995
Springer
Performance evaluation studies are to be an integral part of the design and tuning of parallel applications. We propose a hierarchical approach to the systematic characterization o...