55 search results - page 4 / 11 » Mapping of DSP Algorithms on Field Programmable Function Arr... |
147
Voted
ERSA
2009
15 years 16 days ago
2009
Abstract-- The paper presents the implementation of nonlinear least-squares regression in a Field Programmable Gate Array (FPGA) device. The implemented algorithm is very performan...
129
Voted
ICCS
2004
Springer
15 years 8 months ago
2004
Springer
This work discusses an Evolvable Hardware (EHW) platform for the intrinsic evolution of analog electronic circuits. The EHW analog platform, named PAMA-NG (Programmable Analog Mult...
135
Voted
DFT
2006
IEEE
15 years 8 months ago
2006
IEEE
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
94
Voted
DAC
2006
ACM
16 years 3 months ago
2006
ACM
Highly regular, nanodevice based architectures have been proposed to replace pure CMOS based architectures in the emerging post CMOS era. Since bottom-up self-assembly is used to ...
151
Voted
FPGA
2012
ACM
13 years 10 months ago
2012
ACM
In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemente...