83 search results - page 16 / 17 » Matrix scheduler reloaded |
162
Voted
HIPC
2009
Springer
14 years 7 months ago
2009
Springer
The significant growth in computational power of modern Graphics Processing Units(GPUs) coupled with the advent of general purpose programming environments like NVIDA's CUDA,...
ICRA
2005
IEEE
15 years 3 months ago
2005
IEEE
- This paper presents a new control method to drive an array of wet Shape Memory Alloy actuators utilizing a Matrix Manifold and Valve system (MMV). The MMV architecture allows a v...
82
Voted
PADS
2009
ACM
15 years 4 months ago
2009
ACM
Abstract—In this paper we illustrate scalable parallel performance for the Time Warp synchronization protocol on the L and P variants of the IBM Blue Gene supercomputer. Scalable...
93
Voted
CLUSTER
2007
IEEE
15 years 3 months ago
2007
IEEE
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
SPAA
1996
ACM
15 years 1 months ago
1996
ACM
In this paper, we analyze the performance of parallel multithreaded algorithms that use dag-consistent distributed shared memory. Specifically, we analyze execution time, page fau...