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DAC
2010
ACM
15 years 8 months ago
On the costs and benefits of stochasticity in stream processing
With the end of clock-frequency scaling, parallelism has emerged as the key driver of chip-performance growth. Yet, several factors undermine efficient simultaneous use of onchip ...
Raj R. Nadakuditi, Igor L. Markov
MEMOCODE
2008
IEEE
15 years 11 months ago
Virtual prototyping AADL architectures in a polychronous model of computation
While synchrony and asynchrony are two distinct concepts of concurrency theory, effective and formally defined embedded system design methodologies usually mix the best from both...
Ma Yue, Jean-Pierre Talpin, Thierry Gautier
ISCAS
2005
IEEE
121views Hardware» more  ISCAS 2005»
15 years 10 months ago
On-board fault-tolerant SAR processor for spaceborne imaging radar systems
A real-timehigh-performanceand fault-tolerantFPGA-based hardware architecture for the processing of synthetic apertureradar (SAR) images has been developed for advanced spaceborner...
Wai-Chi Fang, C. Le, S. Taft
ISCA
2008
IEEE
136views Hardware» more  ISCA 2008»
15 years 4 months ago
The Design and Performance of a Bare PC Web Server
There is an increasing need for new Web server architectures that are application-centric, simple, small, and pervasive in nature. In this paper, we present a novel architecture f...
Long He, Ramesh K. Karne, Alexander L. Wijesinha
153
Voted
ICASSP
2010
IEEE
15 years 2 months ago
Bandwidth-intensive FPGA architecture for multi-dimensional DFT
Multi-dimensional (MD) Discrete Fourier Transform (DFT) is a key kernel algorithm in many signal processing algorithms, including radar data processing and medical imaging. Althou...
Chi-Li Yu, Chaitali Chakrabarti, Sungho Park, Vija...