Sciweavers

753 search results - page 117 / 151
» Mechanisms for Mapping High-Level Parallel Performance Data
Sort
View
ICPADS
2006
IEEE
15 years 7 months ago
Destination-Based HoL Blocking Elimination
Congestion management is likely to become a critical issue in interconnection networks, as increasing power consumption and cost concerns will lead to the use of smaller networks....
T. Nachiondo, Jose Flich, José Duato
SIGMOD
2012
ACM
226views Database» more  SIGMOD 2012»
13 years 3 months ago
SkewTune: mitigating skew in mapreduce applications
We present an automatic skew mitigation approach for userdefined MapReduce programs and present SkewTune, a system that implements this approach as a drop-in replacement for an e...
YongChul Kwon, Magdalena Balazinska, Bill Howe, Je...
CLUSTER
2008
IEEE
15 years 7 months ago
Live and incremental whole-system migration of virtual machines using block-bitmap
—In this paper, we describe a whole-system live migration scheme, which transfers the whole system run-time state, including CPU state, memory data, and local disk storage, of th...
Yingwei Luo, Binbin Zhang, Xiaolin Wang, Zhenlin W...
PVM
1998
Springer
15 years 5 months ago
SKaMPI: A Detailed, Accurate MPI Benchmark
Abstract. SKaMPI is a benchmark for MPI implementations. Its purpose is the detailed analysis of the runtime of individual MPI operations and comparison of these for di erent imple...
Ralf Reussner, Peter Sanders, Lutz Prechelt, Matth...
SIPS
2008
IEEE
15 years 7 months ago
Unified decoder architecture for LDPC/turbo codes
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
Yang Sun, Joseph R. Cavallaro