753 search results - page 69 / 151 » Mechanisms for Mapping High-Level Parallel Performance Data |
136
click to vote
ICCTA
2007
IEEE
15 years 5 months ago
2007
IEEE
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
117
click to vote
HPCA
2003
IEEE
16 years 1 months ago
2003
IEEE
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
PPOPP
2006
ACM
15 years 7 months ago
2006
ACM
Tiling has proven to be an effective mechanism to develop high performance implementations of algorithms. Tiling can be used to organize computations so that communication costs i...
146
click to vote
ESTIMEDIA
2009
Springer
15 years 8 months ago
2009
Springer
—Real-time encoding of high-definition H.264 video is a challenge to current embedded programmable processors. Emerging stream processing methods supported by most GPUs and progr...
107
click to vote
HPCA
1996
IEEE
15 years 5 months ago
1996
IEEE
Traditional DMA requires the operating system to perform many tasks to initiate a transfer, with overhead on the order of hundreds or thousands of CPU instructions. This paper des...