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» Mechanisms for store-wait-free multiprocessors
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CASES
2001
ACM
15 years 3 months ago
A system-on-a-chip lock cache with task preemption support
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of loc...
Bilge Saglam Akgul, Jaehwan Lee, Vincent John Moon...
DAC
2007
ACM
16 years 24 days ago
The Case for Low-Power Photonic Networks on Chip
Packet-switched networks on chip (NoC) have been advocated as a natural communication mechanism among the processing cores in future chip multiprocessors (CMP). However, electroni...
Assaf Shacham, Keren Bergman, Luca P. Carloni
DATE
2009
IEEE
98views Hardware» more  DATE 2009»
15 years 6 months ago
A real-time application design methodology for MPSoCs
This paper presents a novel technique for the modeling, simulation, and analysis of real-time applications on MultiProcessor Systems-on-Chip (MPSoCs). This technique is based on a...
Giovanni Beltrame, Luca Fossati, Donatella Sciuto
CLUSTER
2008
IEEE
15 years 6 months ago
Predictive models for bandwidth sharing in high performance clusters
Abstract—Using MPI as communication interface, one or several applications may introduce complex communication behaviors over the network cluster. This effect is increased when n...
Jérôme Vienne, Maxime Martinasso, Jea...
ICPADS
2006
IEEE
15 years 5 months ago
Flexible, Low-overhead Event Logging to Support Resource Scheduling
Flexible resource management and scheduling policies require detailed system-state information. Traditional, monolithic operating systems with a centralized kernel derive the requ...
Jan Stoess, Volkmar Uhlig