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» Memory Hierarchy Management for Iterative Graph Structures
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ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
15 years 5 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
ASPLOS
2010
ACM
15 years 6 months ago
Dynamically replicated memory: building reliable systems from nanoscale resistive memories
DRAM is facing severe scalability challenges in sub-45nm technology nodes due to precise charge placement and sensing hurdles in deep-submicron geometries. Resistive memories, suc...
Engin Ipek, Jeremy Condit, Edmund B. Nightingale, ...
ICDM
2005
IEEE
188views Data Mining» more  ICDM 2005»
15 years 5 months ago
Hierarchy-Regularized Latent Semantic Indexing
Organizing textual documents into a hierarchical taxonomy is a common practice in knowledge management. Beside textual features, the hierarchical structure of directories reflect...
Yi Huang, Kai Yu, Matthias Schubert, Shipeng Yu, V...
CODES
2003
IEEE
15 years 4 months ago
A low-cost memory architecture with NAND XIP for mobile embedded systems
NAND flash memory has become an indispensable component in mobile embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cost and ...
Chanik Park, Jaeyu Seo, Sunghwan Bae, Hyojun Kim, ...
CLOUDCOM
2009
Springer
15 years 3 months ago
Cost-Minimizing Scheduling of Workflows on a Cloud of Memory Managed Multicore Machines
Workflows are modeled as hierarchically structured directed acyclic graphs in which vertices represent computational tasks, referred to as requests, and edges represent precedent c...
Nicolas G. Grounds, John K. Antonio, Jeffrey T. Mu...