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» Memory Practices in the Sciences
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ICS
2009
Tsinghua U.
15 years 4 months ago
Computer generation of fast fourier transforms for the cell broadband engine
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
Srinivas Chellappa, Franz Franchetti, Markus P&uum...
ICS
2009
Tsinghua U.
15 years 4 months ago
Cancellation of loads that return zero using zero-value caches
The speed gap between processor and memory continues to limit performance. To address this problem, we explore the potential of eliminating Zero Loads—loads accessing memory loc...
Md. Mafijul Islam, Sally A. McKee, Per Stenstr&oum...
ICALP
2007
Springer
15 years 4 months ago
Checking and Spot-Checking the Correctness of Priority Queues
We revisit the problem of memory checking considered by Blum et al. [3]. In this model, a checker monitors the behavior of a data structure residing in unreliable memory given an a...
Matthew Chu, Sampath Kannan, Andrew McGregor
JLP
2007
95views more  JLP 2007»
14 years 9 months ago
Model checking a cache coherence protocol of a Java DSM implementation
Jackal is a fine-grained distributed shared memory implementation of the Java programming language. It aims to implement Java’s memory model and allows multithreaded Java progr...
Jun Pang, Wan Fokkink, Rutger F. H. Hofman, Ronald...
NN
1998
Springer
14 years 9 months ago
Distributed ARTMAP: a neural network for fast distributed supervised learning
Distributed coding at the hidden layer of a multi-layer perceptron (MLP) endows the network with memory compression and noise tolerance capabilities. However, an MLP typically req...
Gail A. Carpenter, Boriana L. Milenova, Benjamin W...