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ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
16 years 1 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
HPCA
1995
IEEE
15 years 8 months ago
Program Balance and Its Impact on High Performance RISC Architectures
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee...
127
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WOSP
2004
ACM
15 years 10 months ago
Application performance on the Direct Access File System
The Direct Access File System (DAFS) is a distributed file system built on top of direct-access transports (DAT). Direct-access transports are characterized by using remote direct...
Alexandra Fedorova, Margo I. Seltzer, Kostas Magou...
ECRTS
2007
IEEE
15 years 11 months ago
On Scheduling and Real-Time Capacity of Hexagonal Wireless Sensor Networks
Since wireless ad-hoc networks use shared communication medium, accesses to the medium must be coordinated to avoid packet collisions. Transmission scheduling algorithms allocate ...
Shashi Prabh, Tarek F. Abdelzaher
ICDE
2000
IEEE
111views Database» more  ICDE 2000»
16 years 5 months ago
Dynamic Query Scheduling in Data Integration Systems
Execution plans produced by traditional query optimizers for data integration queries may yield poor performance for several reasons. The cost estimates may be inaccurate, the mem...
C. Mohan, Françoise Fabret, Luc Bouganim, P...