3202 search results - page 59 / 641 » Memory access scheduling |
180
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HPCA
2011
IEEE
14 years 7 months ago
2011
IEEE
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...
137
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IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
In this paper, we present a mechanism for automatic management of the memory hierarchy, including secondary storage, in the context of a global address space parallel programming ...
153
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IPPS
2006
IEEE
15 years 10 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
145
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STACS
2005
Springer
15 years 9 months ago
2005
Springer
Abstract. The dynamic page migration problem [4] is defined in a distributed network of n mobile nodes sharing one indivisible memory page of size D. During runtime, the nodes can...
243
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HIPC
2009
Springer
15 years 1 months ago
2009
Springer
The significant growth in computational power of modern Graphics Processing Units(GPUs) coupled with the advent of general purpose programming environments like NVIDA's CUDA,...