3202 search results - page 96 / 641 » Memory access scheduling |
161
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ESTIMEDIA
2008
Springer
15 years 6 months ago
2008
Springer
The relentless increase in multimedia embedded system application requirements as well as improvements in IC design technology have motivated the deployment of chip multiprocessor ...
166
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MICRO
2010
IEEE
15 years 2 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
158
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ISCA
2012
IEEE
13 years 6 months ago
2012
IEEE
Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served serially, exacerbating the h...
141
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ICCD
2001
IEEE
16 years 1 months ago
2001
IEEE
This paper deals with low-energy code generation for a highly optimized digital signal processor designed for mobile communication applications. We present a genetic algorithm bas...
181
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AAAIDEA
2005
IEEE
15 years 10 months ago
2005
IEEE
—Differentiated Service (DiffServ) in combination with Multi-Protocol Label Switching (MPLS) is a promising technology in converting the best-effort Internet into a QoS-capable n...