3202 search results - page 98 / 641 » Memory access scheduling |
137
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ISCA
2010
IEEE
15 years 9 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
148
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VLSID
2007
IEEE
16 years 4 months ago
2007
IEEE
The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall ...
120
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IPPS
2003
IEEE
15 years 9 months ago
2003
IEEE
Our recent work on uniprocessor and single-node multiprocessor (SMP) active memory systems uses address remapping techniques in conjunction with extended cache coherence protocols...
115
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IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
A fundamental challenge in Internet computing (IC) is to efficiently schedule computations having complex interjob dependencies, given the unpredictability of remote machines, in...
106
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RTS
2002
15 years 4 months ago
2002
In this paper, we present the Cello disk scheduling framework for meeting the diverse service requirements of applications. Cello employs a two-level disk scheduling architecture,...