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DAC
2000
ACM
15 years 11 months ago
Memory aware compilation through accurate timing extraction
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...
Peter Grun, Nikil D. Dutt, Alexandru Nicolau
IFL
2001
Springer
146views Formal Methods» more  IFL 2001»
15 years 2 months ago
Optimizations on Array Skeletons in a Shared Memory Environment
Map- and fold-like skeletons are a suitable abstractions to guide parallel program execution in functional array processing. However, when it comes to achieving high performance, i...
Clemens Grelck
VLSISP
2008
159views more  VLSISP 2008»
14 years 10 months ago
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores
The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open re...
Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin...
JUCS
2000
120views more  JUCS 2000»
14 years 10 months ago
Compiler Generated Multithreading to Alleviate Memory Latency
: Since the era of vector and pipelined computing, the computational speed is limited by the memory access time. Faster caches and more cache levels are used to bridge the growing ...
Kristof Beyls, Erik H. D'Hollander
IPPS
2007
IEEE
15 years 4 months ago
Model-Guided Empirical Optimization for Multimedia Extension Architectures: A Case Study
Compiler technology for multimedia extensions must effectively utilize not only the SIMD compute engines but also the various levels of the memory hierarchy: superword registers,...
Chun Chen, Jaewook Shin, Shiva Kintali, Jacqueline...