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MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
14 years 10 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
RTCSA
1999
IEEE
15 years 4 months ago
Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems
Abstract. We present an approach to static priority preemptive process scheduling for the synthesis of hard realtime distributed embedded systems where communication plays an impor...
Paul Pop, Petru Eles, Zebo Peng
ADBIS
2005
Springer
120views Database» more  ADBIS 2005»
15 years 5 months ago
Extensible Canonical Process Model Synthesis Applying Formal Interpretation
The current period of IT development is characterized by an explosive growth of diverse information representation languages. Applying integration and composition of heterogeneous ...
Leonid A. Kalinichenko, Sergey A. Stupnikov, Nikol...
ESORICS
2006
Springer
15 years 3 months ago
Policy-Driven Memory Protection for Reconfigurable Hardware
Abstract. While processor based systems often enforce memory protection to prevent the unintended sharing of data between processes, current systems built around reconfigurable har...
Ted Huffmire, Shreyas Prasad, Timothy Sherwood, Ry...
ASPDAC
2009
ACM
139views Hardware» more  ASPDAC 2009»
15 years 6 months ago
Hardware-dependent software synthesis for many-core embedded systems
Abstract— This paper presents synthesis of Hardware Dependent Software (HdS) for multicore and many-core designs using Embedded System Environment (ESE). ESE is a tool set, devel...
Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho...