40 search results - page 4 / 8 » Memory-Aware Application Mapping on Coarse-Grained Reconfigu... |
84
Voted
APCSAC
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper introduces a method which can be used to map applications written in a high level source language program, like C, to a coarse grain reconfigurable architecture, MONTIU...
FPL
2010
Springer
14 years 7 months ago
2010
Springer
Abstract--Efficient storage in spatial processors is increasingly important as such devices get larger and support more concurrent operations. Unlike sequential processors that rel...
ARC
2007
Springer
15 years 1 months ago
2007
Springer
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
IPPS
2007
IEEE
15 years 3 months ago
2007
IEEE
This paper presents the performance improvements and the energy reductions by coupling a highperformance coarse-grained reconfigurable data-path with a microprocessor in a generic...
83
Voted
VLSISP
2008
14 years 9 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...