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ICPADS
2006
IEEE
15 years 9 months ago
SPM Conscious Loop Scheduling for Embedded Chip Multiprocessors
One of the major factors that can potentially slow down widespread use of embedded chip multiprocessors is lack of efficient software support. In particular, automated code paral...
Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Tayl...
ICRA
2006
IEEE
190views Robotics» more  ICRA 2006»
15 years 9 months ago
An Integrated Approach to Inverse Kinematics and Path Planning for Redundant Manipulators
— We propose a novel solution to the problem of inverse kinematics for redundant robotic manipulators for the purposes of goal selection for path planning. We unify the calculati...
Dominik Bertram, James Kuffner, Rüdiger Dillm...
IJCNN
2006
IEEE
15 years 9 months ago
Venn-like models of neo-cortex patches
— This work presents a new architecture of artificial neural networks – Venn Networks, which produce localized activations in a 2D map while executing simple cognitive tasks. T...
Fernando Buarque de Lima Neto, Philippe De Wilde
MEMOCODE
2006
IEEE
15 years 9 months ago
Latency-insensitive design and central repetitive scheduling
The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the...
Julien Boucaron, Robert de Simone, Jean-Vivien Mil...
RTSS
2006
IEEE
15 years 9 months ago
Run-Time Services for Hybrid CPU/FPGA Systems on Chip
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
Jason Agron, Wesley Peck, Erik Anderson, David L. ...
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