27 search results - page 3 / 6 » Methodologies for Tolerating Cell and Interconnect Faults in... |
FPL
2005
Springer
13 years 11 months ago
2005
Springer
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate ...
NPC
2004
Springer
13 years 11 months ago
2004
Springer
Massively parallel computing systems are being built with thousands of nodes. Because of the high number of components, it is critical to keep these systems running even in the pre...
GLVLSI
2005
IEEE
13 years 12 months ago
2005
IEEE
A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-ba...
ET
2002
13 years 6 months ago
2002
As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay viol...
FPGA
2006
ACM
13 years 10 months ago
2006
ACM
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...