27 search results - page 5 / 6 » Methodologies for Tolerating Cell and Interconnect Faults in... |
DATE
2005
IEEE
13 years 12 months ago
2005
IEEE
attributed to the high regularity of memories, PAs and FPGAs, and the ease with which they can be tested and reconfigured to avoid faulty elements. Digital microfluidicsbased bioch...
DATE
2005
IEEE
13 years 12 months ago
2005
IEEE
Technology Roadmap for Semiconductors (ITRS) clearly identifies the integration of electrochemical and electrobiological techniques as one of the system-level design challenges tha...
JIRS
2007
13 years 6 months ago
2007
This paper presents a methodology for the realization of intelligent, task-based reconfiguration of the computational hardware for mobile robot applications. Task requirements are ...
ICCAD
2005
IEEE
14 years 3 months ago
2005
IEEE
— Increasingly prominent variational effects impose imminent threat to the progress of VLSI technology. This work explores redundancy, which is a well-known fault tolerance techn...
FPGA
2009
ACM
14 years 1 months ago
2009
ACM
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...