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ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
15 years 5 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
SIPS
2008
IEEE
15 years 6 months ago
Efficient mapping of advanced signal processing algorithms on multi-processor architectures
Modern microprocessor technology is migrating from simply increasing clock speeds on a single processor to placing multiple processors on a die to increase throughput and power pe...
Bhavana B. Manjunath, Aaron S. Williams, Chaitali ...
MIDDLEWARE
2010
Springer
14 years 10 months ago
Kevlar: A Flexible Infrastructure for Wide-Area Collaborative Applications
Abstract. While Web Services ensure interoperability and extensibility for networked applications, they also complicate the deployment of highly collaborative systems, such as virt...
Qi Huang, Daniel A. Freedman, Ymir Vigfusson, Ken ...
SBACPAD
2008
IEEE
206views Hardware» more  SBACPAD 2008»
15 years 6 months ago
A High Performance Massively Parallel Approach for Real Time Deformable Body Physics Simulation
Single processor technology has been evolving across last decades, but due to physical limitations of chip manufacturing process, the industry is pursuing alternatives to sustain ...
Thiago S. M. C. de Farias, Mozart W. S. Almeida, J...
IPPS
2007
IEEE
15 years 6 months ago
A Cost-Effective, High Bandwidth Server I/O network Architecture for Cluster Systems
In this paper we present a cost-effective, high bandwidth server I/O network architecture, named PaScal (Parallel and Scalable). We use the PaScal server I/O network to support da...
Hsing-bung Chen, Gary Grider, Parks Fields