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SPDP
1991
IEEE
15 years 1 months ago
Local vs. global memory in the IBM RP3: experiments and performance modelling
A number of experiments regarding the placement of instructions, private data and shared data in the Non-Uniform-Memory-Access multiprocessor, RP3 has been performed. Three Scient...
Mats Brorsson
CLUSTER
2005
IEEE
14 years 11 months ago
SymbioticSphere: Towards an Autonomic Grid Network System
This paper describes SymbioticSphere, a novel biologically-inspired architecture that allows grid systems (application services and middleware platforms) to be scalable and adapti...
Paskorn Champrasert, Chonho Lee, Junichi Suzuki
75
Voted
DATE
2006
IEEE
100views Hardware» more  DATE 2006»
15 years 3 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
IPPS
2007
IEEE
15 years 4 months ago
A General Purpose Partially Reconfigurable Processor Simulator (PReProS)
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
Alisson Vasconcelos De Brito, Matthias Kühnle...
68
Voted
HPCA
2008
IEEE
15 years 10 months ago
An OS-based alternative to full hardware coherence on tiled CMPs
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
Christian Fensch, Marcelo Cintra