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HPCA
2002
IEEE
15 years 10 months ago
Loose Loops Sink Chips
This paper explores the concept of micro-architectural loops and discusses their impact on processor pipelines. In particular, we establish the relationship between loose loops an...
Eric Borch, Eric Tune, Srilatha Manne, Joel S. Eme...
IPPS
2007
IEEE
15 years 4 months ago
A Near-optimal Solution for the Heterogeneous Multi-processor Single-level Voltage Setup Problem
A heterogeneous multi-processor (HeMP) system consists of several heterogeneous processors, each of which is specially designed to deliver the best energy-saving performance for a...
Tai-Yi Huang, Yu-Che Tsai, Edward T.-H. Chu
EUROPAR
2004
Springer
15 years 3 months ago
Large-Scale Deployment in P2P Experiments Using the JXTA Distributed Framework
The interesting properties of P2P systems (high availability despite peer volatility, support for heterogeneous architectures, high scalability, etc.) make them attractive for dist...
Gabriel Antoniu, Luc Bougé, Mathieu Jan, S&...
HPCA
2004
IEEE
15 years 10 months ago
Exploiting Prediction to Reduce Power on Buses
We investigate coding techniques to reduce the energy consumed by on-chip buses in a microprocessor. We explore several simple coding schemes and simulate them using a modified Si...
Victor Wen, Mark Whitney, Yatish Patel, John Kubia...
IEEEPACT
2003
IEEE
15 years 3 months ago
Redeeming IPC as a Performance Metric for Multithreaded Programs
Recent work has shown that multithreaded workloads running in execution-driven, full-system simulation environments cannot use instructions per cycle (IPC) as a valid performance ...
Kevin M. Lepak, Harold W. Cain, Mikko H. Lipasti