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ITC
2000
IEEE
104views Hardware» more  ITC 2000»
15 years 9 months ago
Application of deterministic logic BIST on industrial circuits
We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for...
Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P....
DAC
1996
ACM
15 years 9 months ago
Test Point Insertion: Scan Paths through Combinational Logic
We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses th...
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-T...
DSN
2008
IEEE
15 years 6 months ago
An accurate flip-flop selection technique for reducing logic SER
The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In...
Eric L. Hill, Mikko H. Lipasti, Kewal K. Saluja
ESSCIRC
2011
93views more  ESSCIRC 2011»
14 years 4 months ago
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 volta
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomu...
KBSE
2003
IEEE
15 years 10 months ago
On the automatic evolution of an OS kernel using temporal logic and AOP
Automating software evolution requires both identifying precisely the affected program points and selecting the appropriate modification at each point. This task is particularly ...
Rickard A. Åberg, Julia L. Lawall, Mario S&u...