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130
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ISHPC
2003
Springer
15 years 6 months ago
Code and Data Transformations for Improving Shared Cache Performance on SMT Processors
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
Dimitrios S. Nikolopoulos
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
15 years 5 months ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...
122
Voted
ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
15 years 5 months ago
Using a User-Level Memory Thread for Correlation Prefetching
This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main ...
Yan Solihin, Josep Torrellas, Jaejin Lee
90
Voted
MICRO
2002
IEEE
108views Hardware» more  MICRO 2002»
15 years 5 months ago
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
We describe the design, analysis, and performance of an on–line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MC...
Greg Semeraro, David H. Albonesi, Steve Dropsho, G...
99
Voted
CDC
2009
IEEE
152views Control Systems» more  CDC 2009»
15 years 5 months ago
Distributed image-based 3-D localization of camera sensor networks
— We consider the problem of distributed estimation of the poses of N cameras in a camera sensor network using image measurements only. The relative rotation and translation (up ...
Roberto Tron, René Vidal