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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
15 years 8 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
WWW
2010
ACM
15 years 6 months ago
A scalable machine-learning approach for semi-structured named entity recognition
Named entity recognition studies the problem of locating and classifying parts of free text into a set of predefined categories. Although extensive research has focused on the de...
Utku Irmak, Reiner Kraft
HPCA
2009
IEEE
15 years 6 months ago
Reconciling specialization and flexibility through compound circuits
While parallelism and multi-cores are receiving much attention as a major scalability path, customization is another, orthogonal and complementary, scalability path which can targ...
Sami Yehia, Sylvain Girbal, Hugues Berry, Olivier ...
ISPD
2009
ACM
112views Hardware» more  ISPD 2009»
15 years 6 months ago
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs
The multiple-supply voltage (MSV) design style has been extensively applied to mitigate dynamic-power consumption. The MSV design paradigm, however, brings many crucial challenges...
Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang
SENSYS
2009
ACM
15 years 6 months ago
Low-power clock synchronization using electromagnetic energy radiating from AC power lines
Clock synchronization is highly desirable in many sensor networking applications. It enables event ordering, coordinated actuation, energy-efficient communication and duty cyclin...
Anthony Rowe, Vikram Gupta, Ragunathan Rajkumar