70 search results - page 10 / 14 » Minimizing average flow-time under knapsack constraint |
ICCAD
2004
IEEE
15 years 7 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
FPGA
2001
ACM
15 years 2 months ago
2001
ACM
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
JOIN
2007
14 years 10 months ago
2007
This paper is devoted to the following incremental problem. Initially, a graph and a distinguished subset of vertices, called initial group, are given. This group is connected by ...
WOWMOM
2005
ACM
15 years 3 months ago
2005
ACM
— We consider the design of optimal strategies for joint power adaptation, rate adaptation and scheduling in a multi-hop wireless network. Most existing strategies control either...
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VTS
2006
IEEE
15 years 4 months ago
2006
IEEE
— In this paper, an algorithm for scan vector ordering, PEAKASO, is proposed to minimize the peak temperature during scan testing. Given a circuit with scan and the scan vectors,...