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128
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ASIAN
2007
Springer
157views Algorithms» more  ASIAN 2007»
15 years 8 months ago
A Logical Framework for Evaluating Network Resilience Against Faults and Attacks
Abstract. We present a logic-based framework to evaluate the resilience of computer networks in the face of incidents, i.e., attacks from malicious intruders as well as random faul...
Elie Bursztein, Jean Goubault-Larrecq
RTS
2008
131views more  RTS 2008»
15 years 1 months ago
Formal verification of multitasking applications based on timed automata model
The aim of this paper is to show, how a multitasking application running under a real-time operating system compliant with an OSEK/VDX standard can be modeled by timed automata. Th...
Libor Waszniowski, Zdenek Hanzálek
134
Voted
DFG
2004
Springer
15 years 5 months ago
Verification of PLC Programs Given as Sequential Function Charts
Programmable Logic Controllers (PLC) are widespread in the manufacturing and processing industries to realize sequential procedures and to avoid safety-critical states. For the spe...
Nanette Bauer, Sebastian Engell, Ralf Huuck, Sven ...
CAISE
2008
Springer
15 years 3 months ago
Formal Modeling and Discrete-Time Analysis of BPEL Web Services
Abstract. Web services are increasingly used for building enterprise information systems according to the Service Oriented Architecture (Soa) paradigm. We propose in this paper a t...
Radu Mateescu, Sylvain Rampacek
106
Voted
CEC
2008
IEEE
15 years 8 months ago
Finding liveness errors with ACO
Abstract— Model Checking is a well-known and fully automatic technique for checking software properties, usually given as temporal logic formulae on the program variables. Most o...
J. Francisco Chicano, Enrique Alba