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» Model Reuse through Hardware Design Patterns
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ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
15 years 2 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
DATE
2010
IEEE
154views Hardware» more  DATE 2010»
14 years 8 months ago
A proposal for real-time interfaces in SPEEDS
Abstract—The SPEEDS project is aimed at making rich components models (RCM) into a mature framework in all phases of the design of complex distributed embedded systems. The RCM m...
Purandar Bhaduri, Ingo Stierand
IJCSA
2008
102views more  IJCSA 2008»
14 years 9 months ago
New Information and Communication Technologies for the Teaching of Computer Graphic Design
Within the computer aided design (CAD) teaching framework, new information and communication technologies (ICT's) are being set through new tools and methodological changes: ...
G. del Rio-Cidoncha, J. Martinez-Palacios, E. Mart...
COMPSAC
2004
IEEE
15 years 1 months ago
A Development Framework for Rapid Meta-Heuristics Hybridization
While meta-heuristics are effective for solving large-scale combinatorial optimization problems, they result from time-consuming trial-and-error algorithm design tailored to speci...
Hoong Chuin Lau, Wee Chong Wan, Min Kwang Lim, Ste...
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
15 years 3 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen