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» Model checking SystemC designs using timed automata
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DT
2006
180views more  DT 2006»
13 years 6 months ago
A SystemC Refinement Methodology for Embedded Software
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
Jérôme Chevalier, Maxime de Nanclas, ...
FDL
2005
IEEE
13 years 12 months ago
Incorporating SystemC in Analog/Mixed-Signal Design Flow
In today’s flows, there is still a gap between system level description and hardware implementation, especially for analog/RF building blocks. SystemC-AMS or co-simulations have...
Patrick Birrer, Walter Hartong
IPPS
2003
IEEE
13 years 11 months ago
System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC
To cope with the increasing demand for higher computational power and flexibility, dynamically reconfigurable blocks become an important part inside a system-on-chip. Several meth...
Antti Pelkonen, Kostas Masselos, Miroslav Cup&aacu...
FORMATS
2004
Springer
13 years 11 months ago
Symbolic Model Checking for Probabilistic Timed Automata
Probabilistic timed automata are timed automata extended with discrete probability distributions, and can be used to model timed randomised protocols or faulttolerant systems. We ...
Marta Z. Kwiatkowska, Gethin Norman, Jeremy Sprost...
SIES
2010
IEEE
13 years 4 months ago
Verification of a CAN bus model in SystemC with functional coverage
Abstract--Many heterogeneous embedded systems, for example industrial automation and automotive applications, require hard-real time constraints to be exhaustively verified - which...
Christoph Kuznik, Gilles B. Defo, Wolfgang Mü...